The present invention relates to a novel non-volatile memory capable of recording multiple bit information in a single memory cell having a non-conductive charge trapping gate.
Non-volatile memories that utilize semiconductor are in widespread use as information recording media on account of being capable of retaining information even if the power supply is OFF, and being capable of read-out at high speeds. In recent years, non-volatile memories have been employed in mobile information terminals, and as recording media for digital cameras and for digital music in the form of MP3 data, for example.
Non-volatile memories, such as the flash memories that are currently in widespread use, are constructed so as to have a conductive floating gate and control gate on a channel region between a source region and drain region. A non-volatile memory of this kind is constituted such that a floating gate is buried in a gate insulating film, and one-bit information is stored according to whether charge is or is not injected into this floating gate. Due to the fact that these non-volatile memories of widespread usage have a floating gate that is electrically conductive, when defects, however small, are present in the gate oxide film, electrons in the floating gate are all lost via these defects. There is therefore a problem in that high reliability is unattainable.
Other than the non-volatile memories of widespread usage mentioned above, a new type of non-volatile memory has been proposed that is provided with a non-conductive charge trapping gate in place of a floating gate, and that stores two-bit information by causing charge beside the source and beside the drain to be trapped. For example, a non-volatile memory of this kind is disclosed in the PCT application W099/07000 xe2x80x9cTwo Bit Non-volatile Electrically Erasable and Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trappingxe2x80x9d. Since this non-volatile memory has a trapping gate that is non-conductive, the probability of loss of electrons injected locally is low, whereby it is possible to attain high reliability.
FIG. 1 shows the constitution of the above-mentioned conventional two-bit non-volatile memory. FIG. 1(1) is a cross-sectional view thereof, and FIG. 1(2) is an equivalent circuit diagram thereof. Source-drain regions SD1, SD2 are formed at the surface of a silicon substrate 1, and a trapping gate TG formed from a silicon nitride film or the like, and a control gate CG of a conductive material, are formed on the channel region. The trapping gate TG is buried in the insulating film 2 made of silicon oxide film or the like, to thereby form a composite MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) structure. By utilizing the difference in bandgap between the silicon nitride film and silicon oxide film, it is possible to cause charge to be trapped and retained in the silicon nitride film.
The special constitution of this non-volatile memory is a trapping gate TG consisting of a non-conductive substance such as a dielectric material, for example, and, in a case in which charge is injected into this trapping gate TG, charge within the trapping gate is unable to move. As a result, it is possible to make a distinction between a case in which charge is injected in the vicinity of the first source-drain region SD1, and a case in which charge is injected in the vicinity of the second source-drain region SD2, and it is thus possible to record two-bit data.
FIG. 1(2) is an equivalent circuit diagram for the above-mentioned two-bit non-volatile memory. Since the trapping gate TG is non-conductive, this trapping gate TG is equivalent to a constitution in which separate MOS transistors are respectively formed in a first trapping gate region TSD1 in the vicinity of the first source-drain region SD1, and in a second trapping gate region TSD2 in the vicinity of the second source-drain region SD2. Further, in the course of the above-described read-out and programming (write) operations, the first and second source-drain regions SD1, SD2 are used either as source regions or drain regions, and these source-drain regions SD1, SD2 are therefore referred to, in this specification, as the first source-drain region SD1 and the second source-drain region SD2, respectively.
FIG. 2 illustrates programming, erasure and read-out of a conventional two-bit non-volatile memory. The voltage applied to the first source-drain region SD1 is called as V(SD1), the voltage applied to the second source-drain region SD2 is called as V(SD2), and the voltage applied to the control gate is called as Vg.
As shown in FIG. 2(1), the programming (write) of the non-volatile storage memory is executed by applying voltages Vg=10V, V(SD1)=0V, V(SD2)=6V, for example, to inject hot electrons produced in the vicinity of the second source-drain region SD2 into the second trapping gate region TSD2 close to the second source-drain region SD2.
In addition, in the course of an erase operation, the voltage applied to the control gate CG is such that Vg=xe2x88x925V, and 5V is applied to the first or second source-drain region SD1 or SD2, or to both the first source-drain region SD1 and the second source-drain region SD2, to extract electrons from the trapping gate TG by utilizing the FN tunnel effect (the Fowler-Nordheim Tunnel effect). At the same time, hot holes produced in the vicinity of the source-drain regions SD1 and SD2, are injected into the trapping gate TG, so that the charge is neutralized within the trapping gate TG.
Next, the read-out operation involves the application of a voltage, whose bias is the reverse of the voltage of the programming operation, between the first and second source-drain regions SD1, SD2, to detect whether or not electrons are trapped in the second trapping gate region TSD2. In other words, in order to read out the state of the second trapping gate region TSD2, voltages applied are Vg=3V, V(SD1)=1.6V, V(SD2)=0V, for example. Here, as shown in FIG. 2(3), when electrons are present in the second trapping gate region TSD2 in the vicinity of the second source-drain region SD2, the channel below the gate does not extend so as to touch the second source-drain region SD2, and, consequently, a channel current does not flow (0 data storage state). Conversely, as shown in FIG. 2(4), when electrons are not present in the second trapping gate region TSD2 in the vicinity of the second source-drain region SD2, the channel reaches to the second source-drain region SD2, and, consequently, a channel current flows (1 data storage state). It is thus possible to detect whether or not there is an accumulation of electrons in the second trapping gate region TSD2, by detecting the ON and OFF of a cell transistor, that is, the existence of a current.
Furthermore, in read-out of the non-volatile storage memory, when, as shown in FIG. 2(5), voltages applied are: Vg=3V, V(SD1)=0,V(SD2)=1.6V, i. e. when the voltage application state between the first and second source-drain regions is the reverse of that in FIG. 2(3) mentioned above, even if electrons are, for example, present in the second trapping gate region TSD2, the state is the same as a MOS transistor whose channel is pinched off, and a channel current flows. Therefore, in a voltage application state of this kind, it is possible to detect whether or not there is an accumulation of electrons in the first trapping gate region TSDL in the vicinity of the first source-drain region SD1, irrespective of the existence of electrons in the second trapping gate region TSD2.
As described above, a conventional memory is capable of recording two-bit information by means of the accumulation or non-accumulation of electrons in the nitride film region TSD1 in the vicinity of the first source-drain region SD1 and in the nitride film region TSD2 in the vicinity of the second source-drain region SD2. As a result, a conventional memory of this kind is advantageous by virtue of affording a larger capacity and a cost reduction per chip as a result of a reduced chip surface area.
FIG. 3 shows a state in which two-bit information is recorded in the above-mentioned non-volatile memory. In the figure, black spots represent electrons. FIG. 3(1) shows a state data=11 in which electrons are not captured in either of the first or second trapping gate regions TSD1, TSD2. FIG. 3(2) shows a state data=01 in which electrons are captured in the second trapping gate region TSD2. FIG. 3(3) shows a state data=00 in which electrons are captured in the first and second trapping gate regions TSD1,TSD2. Further, FIG. 3(4) shows a state data=10 in which electrons are captured in the first trapping gate region TSD1.
The above-mentioned two-bit non-volatile memory is capable of storing two bits in a single memory cell, and is therefore advantageous by virtue of having a large capacity. However, the demand for a large capacity placed on the most recent non-volatile memories surpasses this single-cell/two-bit storage capacity. In other words, when there is a requirement for the recording of still image data, of music data, or even of moving image data, it is desirable to be able to record an even greater number of bits in a single memory cell.
An object of the present invention is to provide a novel non-volatile memory capable of recording three-bit information in a single memory cell.
A further object of the present invention is to provide a read-out method, a programming method, and an erase method, or the like, for a novel non-volatile memory capable of recording three-bit information in a single memory cell.
In order to achieve the above-mentioned objects, one aspect of the present invention is a non-volatile memory which has: first and second source-drain regions at the surface of a semiconductor substrate; and a non-conductive trapping gate, in an insulating film, and a conductive control gate, which are formed on a channel region between these first and second source-drain regions. Further, the non-volatile memory according to the present invention has a first or second state in which, as a result of the application of a voltage between the first and second source-drain regions, hot electrons produced in the vicinity of the first or second source-drain region are locally captured in a first or second trapping gate region in the vicinity of the first and second source-drain regions, respectively. The non-volatile memory according to the present invention also has a third state in which, as a result of the application of a voltage between the control gate and the channel region, electrons (or charge) are (is) injected into the entire trapping gate.
According to whether or not the above-mentioned third state is adopted, one-bit information can be recorded, and according to whether or not the first and second states are adopted, two-bit information can be recorded. Consequently, information totaling three bits can be recorded in a single memory cell.
In order to achieve the above-mentioned objects, another aspect of the present invention is a non-volatile memory for recording multiple bit information, having: first and second source-drain regions formed at the surface of a semiconductor substrate; and a first insulating layer, a non-conductive trapping gate, a second insulating layer, and a control gate, which are formed on a channel region between the first and second source-drain regions, wherein the non-volatile memory for recording multiple bit information has a first state, in which charge is trapped locally in the above-mentioned trapping gate, and a second state, in which charge is injected into the whole of the above-mentioned trapping gate.
According to the present invention, it is possible to record data that differ in a case where electrons are injected into the whole of the non-conductive trapping gate, and in a case where electrons are injected locally therein. By providing a plurality of positions for local injection, it is possible to record data in greater numbers.
The above-mentioned preferred embodiment of the invention is characterized in that, in writing to the first state, a predetermined voltage is applied between the first and second source-drain regions to inject hot electrons produced in the channel region; and, in writing to the second state, a predetermined voltage is applied between the semiconductor substrate and the control gate to perform tunnel injection of charge.
The above-mentioned preferred embodiment of the invention is characterized in that an erase operation is performed by applying a predetermined erase voltage between the semiconductor substrate and the control gate to extract charge present in the whole of the trapping gate or in localized regions of the trapping gate.
The above-mentioned preferred embodiment of the invention is characterized by having a first read-out voltage, a second read-out voltage, and a third read-out voltage, which differ in sequential order, and in that the second read-out voltage is applied to the control gate to perform read-out to detect the existence of the second state, and, the first or third read-out voltage is applied to the control gate to perform read-out to detect the existence of the first state.
In order to achieve the above-mentioned objects, yet another aspect of the present invention is a non-volatile memory for recording multiple bit information, having: first and second source-drain regions formed at the surface of a semiconductor substrate; and a first insulating layer, a non-conductive trapping gate, a second insulating layer, and a control gate, which are formed on a channel region between the first and second source-drain regions, wherein the non-volatile memory for recording multiple bit information has a first state, in which charge is trapped in a first trapping gate region in the trapping gate, in the vicinity of the first source-drain region, a second state, in which charge is trapped in a second trapping gate region in the trapping gate, in the vicinity of the second source-drain region, and a third state in which charge is injected into the whole of the trapping gate.